Time - Constrained Code Compaction for DSPsRainer

| This paper addresses instruction-level paral-lelism in code generation for DSPs. In presence of potential parallelism, the task of code generation includes code com-paction, which parallelizes primitive processor operations under given dependency and resource constraints. Furthermore , DSP algorithms in most cases are required to guarantee real-time response. Since the exact execution speed of a DSP program is only known after compaction, real-time constraints should be taken into account during the com-paction phase. While previous DSP code generators rely on rigid heuristics for compaction, we propose a novel approach to exact local code compaction based on an Integer Programming model, which handles time constraints. Due to a general problem formulation, the IP model also captures encoding restrictions and handles instructions having alternative encodings and side eeects, and therefore applies to a large class of instruction formats. Capabilities and limitations of our approach are discussed for diierent DSPs.